The present invention relates to integrated semiconductor structures, and more particularly to an integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal. The present invention also relates to a method of forming such an integrated semiconductor structure.
In the semiconductor industry, it has become more and more difficult in recent years to improve device performance. Mobility enhancement is a known way to improve complementary metal oxide semiconductor (CMOS) device performance. For example, it is known that the electron and hole mobility are affected by the wafer surface orientations as well as the current flow directions. This is because of the anisotropic effective mass behaviors of the inversion layer carriers.
Currently, CMOS devices are formed on a semiconductor wafer that is based on a (100) surface orientation, i.e., crystal plane, with a notch or wafer flat located at the <011> direction. Such a wafer is shown, for example, in FIG. 1A. The surface orientation is defined as the surface normal vector out of the crystal plane of the semiconductor wafer. The standard notation for crystal planes is illustrated in FIGS. 2A, 2B and 2C. The current direction of a MOSFET can be designed at device layout. Under normal operation, the MOSFET current always flows from the source to the drain side modulated by the gate terminal. Therefore, the current flow direction can be controlled by rotating the PC (i.e., polysilicon mask) and RX (i.e., active silicon) masks with respect to the wafer notch.
FIG. 1B is another pictorial representation of a semiconductor wafer having a (100) surface orientation with a notch located at the <011> direction. For a (100) oriented semiconductor wafer, the current flow is insensitive to the current flow directions, if polySi gates are laid out either parallel or perpendicular to the wafer notch.
It is also known in the semiconductor industry that the substantial enhancement of hole mobility (2.7×) can be achieved by using a (110) surface-oriented semiconductor wafer. The enhancement factor is directional dependent. For example, there is more enhancement for the <110> direction than that of the <100> direction. However, electron mobility is known to be degraded in a (110) surface oriented wafer by a comparable percentage. This electron mobility degradation on a (110) wafer is also directional dependent. For example, there is less degradation from the <100> direction than that of the <110> direction.
In view of the state of the art mentioned above, there is a need for providing semiconductor substrate engineering for obtaining CMOS devices having optimum performance.